Empower Logo

Work package 4: Double-sided Cu wafer plating equipment and process development

Research objectives of Work package 4

The novel concept for embedding of high power components proposed in EmPower is based on the process technology used in the PCB industry. Galvanic plated copper interconnections are the basis for vertical connectivity. A perfect copper interface is crucial for a highly reliable connection in a PCB. In the case of the ECP power core the embedded power components need well-defined copper terminations on both sides, as well as tight thickness tolerances and a copper surface with a defined surface roughness. Another parameter for high yield production of this technology is the component flatness. Component flatness becomes very critical with increasing die size and further reduction of the thickness.

All semiconductor suppliers have with the existing sequential plating process big challenges in component warpage. Only a simultaneous double-sided plating process with a well-controlled plating equipment can offer a solution for this problem. During the setup of the proposed EmPower project this lack of capability became more and more obvious. Today no semiconductor house offers double-sided copper plated power components. Hence, since the availability of these components is crucial for the implementation of the embedded power concept, the double-sided wafer plater from Atotech will be a crucial equipment for the development and industrialization of the embedded power concept.

Work package 4 will focus on equipment and process development to provide thin 6” and 8” wafers with electrochemically deposited (ECD) copper on both wafer sides. This WP takes also into account foreground (meaning pre-ECD) front end processes as well as background (meaning post-ECD) front end processes. The compatibility between all required process steps has to be a driver for WP4 in order to provide wafers within specification (WP1).
Three types of wafers will be prepared by ST for equipment and process development at Atotech:

  • 8” wafers, with TAIKO ring, targeting IGBTs products
  • 6” wafers, with minimum thickness of 300μm and minimum 150μm, without TAIKO ring, targeting diode products
  • 8” wafers, without TAIKO ring, using a sequential process to process front side and backside subsequently, targeting possibly IGBT products as well as other applications.